Neural and muscular electrical stimulation has been used as an effective method in clinical treatment for neurological and physiological disorders for decades since the first fully electrical based stimulator was reported in early 1930s. In recent years, advanced semiconductor technology is taken advantage of to implement the stimulators for implantable biomedical applications, such as deep brain stimulation (DBS), retinal/cochlear prosthesis, functional electrical stimulation (FES) and brain to brain interface. Power efficiency of these implantable stimulators becomes increasingly important, since the power needs to be minimized to avoid frequent battery changing or to adapt a smaller power transmission coil.
There are basically three stimulation modes for a stimulator: voltage mode, charge mode and current mode. Voltage mode has the highest power efficiency but is rarely used in modern stimulators. The main problem of the voltage mode is that it cannot provide control on the total stimulation charge/energy as the load impedance is varying over time, probe location and stimulation polarity. The uncontrollable charge/energy may lead to serious safety issue. Charge mode can accurately control the stimulation energy and achieve high power efficiency. However, it requires very large capacitors (˜μF) to deliver sufficient charge/energy into the stimulation site. Thus the charge mode may not be suitable for implantable applications. Current mode is the most popular mode used in the stimulators because of its safety and effectiveness over a wide range of load impedance. Its major drawback is the low power efficiency which is of great importance for these advanced implantable stimulators.
The low power efficiency of current mode stimulators originates from the nature of the bioelectrical interface between the stimulator and the targeted neuron/muscle tissue. Variable or unpredictable site impedance is one of the main sources responsible for the energy efficiency drop. In a stimulation system, for example, a stimulation system 100 as shown in FIG. 1, the load impedance 104 for a stimulator 102 includes stimulation probe impedance and tissue impedance. The load impedance may vary when using different shaped probes 106 or at different stimulation sites 108 when stimulating different body tissue as shown in FIG. 1. Moreover, the load impedance may change over time in the chronic clinical stimulation. Thus, the maximum load impedance must be accommodated in the stimulator design, which means enough voltage compliance must be provided for a certain current level. For example, in the case of 1 mA current stimulation with 10 kΩ resistive load, ideally 10V voltage compliance needs to be provided by the stimulator. In most of the stimulators a fixed high voltage power supply is used to provide the high voltage compliance. In another case, for example when the 10 kΩ load is changing to a smaller value of 1 kΩ for some reason such as switching to other stimulation site or probe movement, assuming the stimulation current is still kept as 1 mA, the power efficiency drops dramatically from ideal 100% to 10%. This power efficiency problem is illustrated in FIG. 1, wherein when the load impedance is high (Rhigh), the Vover-head is small and the wasted power Pw is low. Accordingly, the power efficiency is about 80%. When the load impedance is low (Rlow), the Vover-head is large and the wasted power Pw is high. In that case, the power efficiency is about 20%.
Closed loop configuration is widely used in many stimulation systems. Many research groups are now working to improve the power efficiency for the current mode stimulators based on closed loop supply voltage adaptation method.
In the supply voltage adaptation method (e.g. as shown in FIGS. 2A and 2B), the supply voltage of the output stage VDD_h is varying based on the load impedance. Two important building blocks are required for this method: 1) impedance detection block to acquire the load impedance information and 2) the adaptive supply block (DC-DC convener) to adjust the supply voltage so as to increase the power efficiency.
FIG. 2A shows a diagram of an adaptive power supply stimulator 200. The stimulator 200 includes a digital control block 202, a digital to analog converter 204 (DAC), a high voltage output stage 206 (HVOS), a high voltage (HV) monitoring block 208 and a DC-DC converter 210. The HV monitoring block 208 is used as the impedance detection block, since the voltage on the stimulation electrode is proportional to the load impedance. The voltage across the load is the direct indication of the power efficiency.
FIG. 2B shows a chart 250 illustrating the supply voltage adaptation provided by the adaptive power supply stimulator 200. Using a simplified resistive dummy load, the stimulation signal (e.g. the stimulation current) used in the supply voltage adaptation may have the same stimulation waveform as the voltage 260 on the stimulation electrode, e.g. a square stimulation waveform of the voltage 260. As shown in FIG. 2B, when the voltage 260 on the stimulation electrode is detected to be low, e.g., when low load impedance Rlow is detected wherein the power efficiency is indicated to be about 20% as in FIG. 1 above, the DC-DC converter 210 is used to adjust the supply voltage VDD_h 270 to a lower value. This would help to improve the power efficiency to be about 80%.
In K. Sooksood el al. “A Neural Stimulator Front-End with Arbitrary Pulse Shape, HV Compliance and Adaptive Supply Requiring 0.05 mm2 in 0.35 μm HVCMOS,” in IEEE ISSCC 2011, pp. 306-307, a high voltage comparator is used to detect the output voltage. This voltage comparator is used to control a two-level (20V and 5V) supply for the output stage. The estimated power efficiency for the output stage is from 20% to 90% using 100 μA stimulation current with lms duration on the load impedance ranging from 10 kΩ to 100 kΩ.
The supply voltage adaptation approach normally requires large inductors and consumes a lot of power. In some approaches, inductors and capacitors are required to provide different level of supply voltage to the output stage.
However, the supply voltage adaptation method requires extra circuit block (e.g. DC-DC converter) that causes extra power efficiency drop, and requires large inductors/capacitors for each voltage level and each channel, which may not be suitable for implantable applications. The resolution for voltage levels is also low.